Dr. Aric Shorey
Manager, Commercial Technology
Corning Incorporated
Dr. Aric Shorey joined Corning Incorporated in 2008 as a senior project engineer in the precision machine systems group within Manufacturing, Technology and Engineering. In this role, he was responsible for leading precision finishing projects for a variety of businesses across the company.
In September 2011, Dr. Shorey assumed his current role as Commercial Technology Manager for the Semiconductor Glass Wafer and Interposer programs. He is responsible for leading the technical interface with external industry partners for both of these initiatives.
Dr. Shorey is the author of more than 30 technical publications, an organizing committee member of the Optical Society of America (OSA), Optical Fabrication and Testing (OF&T) and International Microelectronics Assembly and Packaging Society (iMAPS) meetings, and an industry advisory board member for the University of Rochester mechanical engineering department.
Dr. Shorey received his bachelor’s and master’s of science degrees in mechanical engineering and subsequently, his doctoral degree in materials science from the University of Rochester.
Glass Interposer Substrates: Fabrication, Characterization and Modeling
There is growing interest in applying glass as a substrate for 2.5D/3D applications. Glass has many material properties that make it well suited for interposer substrates. Glass based solutions provide significant opportunities for cost benefits by leveraging economies of scale as well as forming substrates at design thickness.
A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, it is expected to have better electrical performance than silicon. Electrical characterization and electrical models demonstrate the advantages of the insulating properties of glass, and its positive impact on functional performance. Further advantages are anticipated in reliability performance, because of the ability to adjust thermal properties such as coefficient of thermal expansion (CTE) of glass. Modeling results demonstrating these improvements will be presented.
Additionally, significant progress has been made in the demonstration of glass interposer fabrication. Fully patterned wafers and panels with through holes and blind holes are being fabricated today. Leveraging existing downstream processes for metallization and electrical distribution on these substrates is also important for cost effectiveness and ease of transition into production. Progress on
demonstrating the ability to leverage existing downstream processes to make functional glass interposers using both through and blind via technology will be presented.