Douglas Yu is a Senior Director of Integrated Interconnect and Package Technology Division of TSMC R&D. During his 17 years at TSMC, he was responsible for the development of TSMC interconnects technology for more than 9 major generations. Douglas established TSMC’s Cu and low-k technologies from 0.18μm node. He led R&D team to deliver the first SoC technology of wafer foundries with Cu/FSG and the first Cu/low-k (K=3.0) of IC industry to mass production from 0.13μm node. These two technologies became industry standard. Dr. Yu also delivered the first Cu/ELK (K=2.55) in the world to production at 45/40nm nodes, along with flip-chip assembly robustness. He developed the first Low-R technology with ELK for TSMC from 28nm node. These advanced interconnect technologies with high performance; high layout density and low power make superior SoC products. Dr. Yu is currently responsible for the R&D of the Integration of Interconnect and Package Technology including advanced Cu/LK interconnect, bumping, packaging and 3D-IC technologies

Prior to this, he was with AT&T Bell Labs at Allentown, PA, USA, where he was involved in the R&D of thin film processes, SRAM local interconnect, Thin-Film-Transistor, low-voltage and low-power device development, and modular Bi-CMOS integration. He received his B.S. and M.S. degrees from National Tsing-Hua University in Physics and Materials Science and Engineering, respectively; and Ph.D. in Materials Science & Engineering from Georgia Institute of Technology, Atlanta, USA.

Dr. Yu has served as general co-chairs of IEEE IITC and chaired ITRS Interconnect conferences. He is a member of the advisory board of IMPACT (International Microsystems, Package, Assembly and Circuits Technology conference). Douglas serves as member of Industrial Advisory Board of Microsystems Industrial Group at Microsystems Technology Laboratories/MIT. He holds more than 250 US patents in the areas of IC and package technology. He has received National Outstanding Invention Award (CAITA), Outstanding Scientific and Technological Worker Award (National Science Council), Industrial Technology Advancement Award (MOEA), National Outstanding R&D Managers (CPMA) and Outstanding Engineers Award (Chinese Institute of Engineer).




	Dr. C.H. Yu / 余振華 Sr. Director TSMC

Profile

Douglas Yu is a Senior Director of Integrated Interconnect and Package Technology Division of TSMC R&D. During his 17 years at TSMC, he was responsible for the development of TSMC interconnects technology for more than 9 major generations. Douglas established TSMC’s Cu and low-k technologies from 0.18μm node. He led R&D team to deliver the first SoC technology of wafer foundries with Cu/FSG and the first Cu/low-k (K=3.0) of IC industry to mass production from 0.13μm node. These two technologies became industry standard. Dr. Yu also delivered the first Cu/ELK (K=2.55) in the world to production at 45/40nm nodes, along with flip-chip assembly robustness. He developed the first Low-R technology with ELK for TSMC from 28nm node. These advanced interconnect technologies with high performance; high layout density and low power make superior SoC products. Dr. Yu is currently responsible for the R&D of the Integration of Interconnect and Package Technology including advanced Cu/LK interconnect, bumping, packaging and 3D-IC technologies Prior to this, he was with AT&T Bell Labs at Allentown, PA, USA, where he was involved in the R&D of thin film processes, SRAM local interconnect, Thin-Film-Transistor, low-voltage and low-power device development, and modular Bi-CMOS integration. He received his B.S. and M.S. degrees from National Tsing-Hua University in Physics and Materials Science and Engineering, respectively; and Ph.D. in Materials Science & Engineering from Georgia Institute of Technology, Atlanta, USA. Dr. Yu has served as general co-chairs of IEEE IITC and chaired ITRS Interconnect conferences. He is a member of the advisory board of IMPACT (International Microsystems, Package, Assembly and Circuits Technology conference). Douglas serves as member of Industrial Advisory Board of Microsystems Industrial Group at Microsystems Technology Laboratories/MIT. He holds more than 250 US patents in the areas of IC and package technology. He has received National Outstanding Invention Award (CAITA), Outstanding Scientific and Technological Worker Award (National Science Council), Industrial Technology Advancement Award (MOEA), National Outstanding R&D Managers (CPMA) and Outstanding Engineers Award (Chinese Institute of Engineer).