


	Mr, Paul Petric Senior Director REBL Systems Group KLA-Tencor Corporation, USA

Profile
- Education: BS Physics & BS Mathematics, Arizona State University, USA
- Experience:
Director of Engineering, eS20 Inspection Division, KLA-Tencor Sr. Staff Engineer, EL-3 & PREVAIL, IBM Corp., USA Engineering manager, Varian USA 31 Patents
Abstract:

Electron Beam Lithography – Roadmap to the Future of HVM Lithography with REBL

Traditionally, EBL (electron beam lithography) has been too slow for most lithography applications outside of the application of mask making. EBL is well suited for mask making because of e-beam’s ability to generate arbitrary patterns and its capability for precision lithography. For direct write on wafers, however, EBL’s throughput has been much too low to be economically viable for HVM (high volume manufacturing). The throughput has been limited by various aspects including data transfer rates, beam deflection, beam settling time, beam current, electron source brightness, beam blur, and resist sensitivity. Advances in EBL have been made which overcome many of these limits. Over the years, EBL has progressed from a single Gaussian beam to a variable shaped beam to projection lithography to massively parallel beams and multiple columns. REBL (Reflective Electron Beam Lithography) is being developed for high throughput electron beam direct write maskless lithography for HVM. By utilizing massively parallel beams and multiple columns, REBL has the potential to achieve throughputs which are capital cost and footprint competitive with optical lithography and overcome many of the historic limits. The REBL system targets critical patterning steps at the 2x and 1x nm HP node and beyond. An advanced CMOS and MEMS chip called a DPG (Digital Pattern Generator) is used to produce over one million individually controlled electron beams. The pattern produced by these beams is demagnified and imaged at the wafer plane to expose the resist. The DPG chip operates at extremely high data rates greater than 1Tbps. Multiple columns each with a DPG chip are used in parallel to further improve the throughput, and clusters of six columns per 300 mm wafer are currently being built. The presentation will focus on three primary topics. A historical perspective of EBL will be given to give a context for the challenges for the future. The role of REBL in the future of EBL and how it will solve the daunting challenges of lithography will be discussed. And finally, recent progress and results of REBL will be shown. This work is supported by DARPA under contract HR0011-07-9-0007. The views, opinions, and/or findings contained in this article/presentation are those of the author/presenter and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense.