


	Mr. Akio Katsumata General Manager Packaging Research & Development Center J-DEVICES CORPORATION

Profile

Education: - Chiba University

Experience: - Chief Specialist, TOSHIBA CORPORATION - Group Manager, TOSHIBA LSI Package Solution CORPORATION

Abstract:

A New Embedded Package Structure and Technology for Next Generation of WLP, The Wafer Level Fan-out Package - WFOP^TM

J-devices is developing a new package structure and technology for the next generation of WLP, the Wafer level Fan-Out Package – WFOP. A face-down mounting type, this package uses a metal plate, e.g. stainless or copper, as the base plate of its redistributed interconnection layer. The redistribution traces fan out of the dies, so that the pincount is not limited by die size as in the case of WLP. The redistributed layer is fabricated in the semi-additive method of copper plating. Manufacturing with this large scale panel substrate, we can achieve higher throughput than with the conventional wafer manufacturing method. Moreover, this new package has several additional benefits, including an ultra thin package, excellent thermal characteristics and reduced noise level, which are made possible by the metal plate. Also the packaging process using such a direct patterning method has potential for new styles of semiconductor packages. The package structure, process flow, design rules, and package characteristics will be provided in this article.