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Mr. Albert Lan / 藍章益 先生 Senior Director Engineering Center -Customer Advanced Packaging, SPIL |
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Profile: |
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| -Education: Master of industrial & manufacturing engineering department, Univ. of Wisconsin, Madison. |
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-Job Experience:
Over 20 years of job experience on semiconductor industry, especially focus on bumping and flip chip advanced assembly technology. |
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| -Now: Senior Director of Customer Advanced Product Division of SPIL (Siliconware, Taiwan), which is 3rd biggest assembly house in the world now. |
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| Abstract: | ||
| A Trace-Embedded Coreless Substrate Technique | ||
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In the presentation, the following several KEY points will be addressed.
1. It is well-known that “thick” substrate core has obviously increased package thickness and also weakened device performance, in term of electrical and thermal points of view. Therefore, as a NEW innovative coreless structure, a substrate with the features of lead-frame trace embedded with pre-molding compound techniques has aroused lots of attention in IC semiconductor industry recently. It has brought not only thin package and device performance benefits, but also tremendous cost-down benefits. 2. Compared with traditional lead-frame types of package (such as QFN, QFP, and so no) with NO trace, the above coreless substrate with trace embedded routing capability can effectively shrink package size to save PCB board space and also shorten wire length to improve device electrical performance. Moreover, its BGA solder ball can enhance better SMT yield & reliability performance as well, which compared with no solder ball in traditional QFN and QFP packages.
3. In the long run, as a ultra low cost solution under certain conditions, the above coreless substrate with multi-trace layer and finer pitch of plating trace capabilities can be easily applied to replace not only wire-bonding FBGA (Fine pitch Ball Grid Array) low-end products, but also FCCSP high-end products.
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