LSI technology has been widely spread in two dimensional over the past three decades and now, it moves into the era of sub-20nm node. From economical view point, however, the development and manufacturing cost for SOC (System on Chip) has become sky-rocketing. The 3D-IC is the one solution to cut the cost without degradation of performances. By separating 3D-LSI technology into elementary technologies such as (1) TSV formation, (2) bump formation, (3) wafer thinning, (4) chip/wafer alignment, and (5) chip/wafer bonding, many methods and many combinations to realize 3D-ICs can be developed. At least the 3D-IC technology hasn’t been unified. The integration methods hinge upon the target application, the supply chain of base chips, the fabrication site, etc. In this Forum, I will update the recent diversity of 3D-IC technologies and talk about the optimum technology selection by taking our 3D integration technology with TSV and bump with few μm dimensions as an example.




	Dr. Makoto Motoyoshi CEO Tohoku-MicroTec Co., Ltd.

Profile

2005-2010 ZyCube Co., Ltd. (President ‘08-’09) R & D for 3D-LSI Integration 1992- Sony Corporation Development of SRAM, NVM(MRAM, FeRAM, RRAM) devices 1982- Hitachi Ltd. Development of SRAM device 1982　Received the M.S. degree from Tohoku University, Sendai, Japan Owned 28 US patents & 81 Jpn. patents


The Way to Select The Optimum 3D IC Technology

Abstract

LSI technology has been widely spread in two dimensional over the past three decades and now, it moves into the era of sub-20nm node. From economical view point, however, the development and manufacturing cost for SOC (System on Chip) has become sky-rocketing. The 3D-IC is the one solution to cut the cost without degradation of performances. By separating 3D-LSI technology into elementary technologies such as (1) TSV formation, (2) bump formation, (3) wafer thinning, (4) chip/wafer alignment, and (5) chip/wafer bonding, many methods and many combinations to realize 3D-ICs can be developed. At least the 3D-IC technology hasn’t been unified. The integration methods hinge upon the target application, the supply chain of base chips, the fabrication site, etc. In this Forum, I will update the recent diversity of 3D-IC technologies and talk about the optimum technology selection by taking our 3D integration technology with TSV and bump with few μm dimensions as an example.